module aib_mac_ch #(
    parameter MCW=640,
    parameter DW=128,
    parameter MW=160
)(
    input mclk,
    input nclk,
    input rst,
    //当前die的坐标值[高三位为diex,低三位为diey]
    input [2:0] CX,  
    input [2:0] CY, 
    // MAC/PHY channel interface
    output [MCW-1:0] data_in_f,
    input [MCW-1:0] data_out_f,
    output m_wr_clk,
    output m_rd_clk,
    output m_ns_fwd_clk,
    input m_fs_fwd_clk,
    output reg ns_mac_rdy,
    input fs_mac_rdy,
    output reg ns_adapter_rstn,
    output reg ms_tx_dcc_dll_lock_req,
    output reg ms_rx_dcc_dll_lock_req,
    output reg sl_tx_dcc_dll_lock_req,
    output reg sl_rx_dcc_dll_lock_req,
    input ms_tx_transfer_en,
    input ms_rx_transfer_en,
    input sl_tx_transfer_en,
    input sl_rx_transfer_en,
    output i_osc_clk,
    // MAC/routers interface to 8 subnet routers
    output all_done,

    input [DW-1:0] i_data0_0,
    input i_valid0_0,
    output o_yummy0_0,
    output [DW-1:0] o_data0_0,
    output o_valid0_0,
    input i_yummy0_0,
    input [DW-1:0] i_data1_0,
    input i_valid1_0,
    output o_yummy1_0,
    output [DW-1:0] o_data1_0,
    output o_valid1_0,
    input i_yummy1_0,

    input [DW-1:0] i_data0_1,
    input i_valid0_1,
    output o_yummy0_1,
    output [DW-1:0] o_data0_1,
    output o_valid0_1,
    input i_yummy0_1,
    input [DW-1:0] i_data1_1,
    input i_valid1_1,
    output o_yummy1_1,
    output [DW-1:0] o_data1_1,
    output o_valid1_1,
    input i_yummy1_1,

    input [DW-1:0] i_data0_2,
    input i_valid0_2,
    output o_yummy0_2,
    output [DW-1:0] o_data0_2,
    output o_valid0_2,
    input i_yummy0_2,
    input [DW-1:0] i_data1_2,
    input i_valid1_2,
    output o_yummy1_2,
    output [DW-1:0] o_data1_2,
    output o_valid1_2,
    input i_yummy1_2,
    
    input [DW-1:0] i_data0_3,
    input i_valid0_3,
    output o_yummy0_3,
    output [DW-1:0] o_data0_3,
    output o_valid0_3,
    input i_yummy0_3,
    input [DW-1:0] i_data1_3,
    input i_valid1_3,
    output o_yummy1_3,
    output [DW-1:0] o_data1_3,
    output o_valid1_3,
    input i_yummy1_3,
    //long wire
    input [DW-1:0] i_data0_4,
    input i_valid0_4,
    output o_yummy0_4,
    output [DW-1:0] o_data0_4,
    output o_valid0_4,
    input i_yummy0_4,
    input [DW-1:0] i_data1_4,
    input i_valid1_4,
    output o_yummy1_4,
    output [DW-1:0] o_data1_4,
    output o_valid1_4,
    input i_yummy1_4,

    input [DW-1:0] i_data0_5,
    input i_valid0_5,
    output o_yummy0_5,
    output [DW-1:0] o_data0_5,
    output o_valid0_5,
    input i_yummy0_5,
    input [DW-1:0] i_data1_5,
    input i_valid1_5,
    output o_yummy1_5,
    output [DW-1:0] o_data1_5,
    output o_valid1_5,
    input i_yummy1_5
);
    reg [15:0] reset_cnt;
    localparam RESET_S1 = 500;
    localparam RESET_S2 = 1000;
    
    assign m_wr_clk=mclk;
    assign m_rd_clk=mclk;
    assign m_ns_fwd_clk=mclk;
    reg cnt;
    always @(posedge mclk) begin
        if(rst)
            cnt<=0;
        else
            cnt<=cnt+1;
    end
    assign i_osc_clk=cnt;
    always @(posedge mclk) begin
        if(rst) begin
            ns_mac_rdy<=0;
            ns_adapter_rstn<=0;
            ms_rx_dcc_dll_lock_req<=0;
            ms_tx_dcc_dll_lock_req<=0;
            reset_cnt<=0;
        end else begin
            ns_mac_rdy<=1;
            reset_cnt<=reset_cnt+1;
            if(reset_cnt>=RESET_S1) begin
                ns_adapter_rstn<=1;
            end
            if(reset_cnt>=RESET_S2) begin
                ms_tx_dcc_dll_lock_req<=1;
                ms_rx_dcc_dll_lock_req<=1;
                sl_tx_dcc_dll_lock_req<=1;
                sl_rx_dcc_dll_lock_req<=1;
            end
        end
    end
    assign all_done=fs_mac_rdy && ns_mac_rdy &&
        ms_tx_transfer_en && ms_rx_transfer_en &&
        sl_tx_transfer_en && sl_rx_transfer_en;
// TEMPLATE
// aib_mac_qua #(
//     .DW (DW ),
//     .MW (MW )
// ) u_aib_mac_qua_T(
//     .clk        (clk        ),
//     .rst        (rst        ),
//     .data_in_f  (data_in_f  ),
//     .data_out_f (data_out_f ),
//     .i_data0    (i_data0_T    ),
//     .i_valid0   (i_valid0_T   ),
//     .o_yummy0   (o_yummy0_T   ),
//     .o_data0    (o_data0_T    ),
//     .o_valid0   (o_valid0_T   ),
//     .i_yummy0   (i_yummy0_T   ),
//     .i_data1    (i_data1_T    ),
//     .i_valid1   (i_valid1_T   ),
//     .o_yummy1   (o_yummy1_T   ),
//     .o_data1    (o_data1_T    ),
//     .o_valid1   (o_valid1_T   ),
//     .i_yummy1   (i_yummy1_T   )
// );
aib_mac_qua #(
    .DW (DW ),
    .MW (MW )
) u_aib_mac_qua_0(
    .mclk(mclk),
    .nclk        (nclk       ),
    .rst        (rst        ),
    .CX         (CX),
    .CY         (CY),
    .data_in_f  (data_in_f[MW-1:0]  ),
    .data_out_f (data_out_f[MW-1:0] ),
    .i_data0    (i_data0_0    ),
    .i_valid0   (i_valid0_0   ),
    .o_yummy0   (o_yummy0_0   ),
    .o_data0    (o_data0_0    ),
    .o_valid0   (o_valid0_0   ),
    .i_yummy0   (i_yummy0_0   ),
    .i_data1    (i_data1_0    ),
    .i_valid1   (i_valid1_0   ),
    .o_yummy1   (o_yummy1_0   ),
    .o_data1    (o_data1_0    ),
    .o_valid1   (o_valid1_0   ),
    .i_yummy1   (i_yummy1_0   ),
    .i_data2    (i_data0_4    ),
    .i_valid2   (i_valid0_4   ),
    .o_yummy2   (o_yummy0_4   ),
    .o_data2    (o_data0_4    ),
    .o_valid2   (o_valid0_4   ),
    .i_yummy2   (i_yummy0_4   )  
);


aib_mac_qua #(
    .DW (DW ),
    .MW (MW )
) u_aib_mac_qua_1(
    .mclk        (mclk       ),
    .nclk(nclk),
    .rst        (rst        ),
    .CX         (CX),
    .CY         (CY),
    .data_in_f  (data_in_f[2*MW-1:MW]  ),
    .data_out_f (data_out_f[2*MW-1:MW] ),
    .i_data0    (i_data0_1    ),
    .i_valid0   (i_valid0_1   ),
    .o_yummy0   (o_yummy0_1   ),
    .o_data0    (o_data0_1    ),
    .o_valid0   (o_valid0_1   ),
    .i_yummy0   (i_yummy0_1   ),
    .i_data1    (i_data1_1    ),
    .i_valid1   (i_valid1_1   ),
    .o_yummy1   (o_yummy1_1   ),
    .o_data1    (o_data1_1    ),
    .o_valid1   (o_valid1_1   ),
    .i_yummy1   (i_yummy1_1   ),
    .i_data2    (i_data0_5    ),
    .i_valid2   (i_valid0_5   ),
    .o_yummy2   (o_yummy0_5   ),
    .o_data2    (o_data0_5    ),
    .o_valid2   (o_valid0_5   ),
    .i_yummy2   (i_yummy0_5   )
);


aib_mac_qua #(
    .DW (DW ),
    .MW (MW )
) u_aib_mac_qua_2(
    .mclk        (mclk       ),
    .nclk(nclk),
    .rst        (rst        ),
    .CX         (CX),
    .CY         (CY),
    .data_in_f  (data_in_f[3*MW-1:2*MW]  ),
    .data_out_f (data_out_f[3*MW-1:2*MW] ),
    .i_data0    (i_data0_2    ),
    .i_valid0   (i_valid0_2   ),
    .o_yummy0   (o_yummy0_2   ),
    .o_data0    (o_data0_2    ),
    .o_valid0   (o_valid0_2   ),
    .i_yummy0   (i_yummy0_2   ),
    .i_data1    (i_data1_2    ),
    .i_valid1   (i_valid1_2   ),
    .o_yummy1   (o_yummy1_2   ),
    .o_data1    (o_data1_2    ),
    .o_valid1   (o_valid1_2   ),
    .i_yummy1   (i_yummy1_2   ),
    .i_data2    (i_data1_4    ),
    .i_valid2   (i_valid1_4   ),
    .o_yummy2   (o_yummy1_4   ),
    .o_data2    (o_data1_4    ),
    .o_valid2   (o_valid1_4   ),
    .i_yummy2   (i_yummy1_4   )
);


aib_mac_qua #(
    .DW (DW ),
    .MW (MW )
) u_aib_mac_qua_3(
    .mclk        (mclk       ),
    .nclk(nclk),
    .rst        (rst        ),
    .CX         (CX),
    .CY         (CY),
    .data_in_f  (data_in_f[4*MW-1:3*MW]  ),
    .data_out_f (data_out_f[4*MW-1:3*MW] ),
    .i_data0    (i_data0_3    ),
    .i_valid0   (i_valid0_3   ),
    .o_yummy0   (o_yummy0_3   ),
    .o_data0    (o_data0_3    ),
    .o_valid0   (o_valid0_3   ),
    .i_yummy0   (i_yummy0_3   ),
    .i_data1    (i_data1_3    ),
    .i_valid1   (i_valid1_3   ),
    .o_yummy1   (o_yummy1_3   ),
    .o_data1    (o_data1_3    ),
    .o_valid1   (o_valid1_3   ),
    .i_yummy1   (i_yummy1_3   ),
    .i_data2    (i_data1_5    ),
    .i_valid2   (i_valid1_5   ),
    .o_yummy2   (o_yummy1_5   ),
    .o_data2    (o_data1_5    ),
    .o_valid2   (o_valid1_5   ),
    .i_yummy2   (i_yummy1_5   )
);

endmodule